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1/9 preliminary data december 2005 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. sts20nhs3ll n-channel 30 v - 0.0032 ? - 20 a so-8 stripfet?iii mosfet plus monolithic schottky table 1: general features typical r ds (on) = 0.0032 ? @ 10v optimal r ds (on) x qg trade-off @ 4.5v reduced switching losses reduced conduction losses reduced diode recovery losses improved junction-case thermal resistance description the sts20nhs3ll utilizes the latest advanced design rules of st?s proprietary stripfet? tech - nology, and a proprietary process for integrating a monolithic schottky diode. the new mosfet is optimized for the most demanding synchronous switch function in dc-dc converter for computer and telecom. applications dc-dc converters for telecom and notebook cpu core synchronous rectification table 2: order codes figure 1: package figure 2: internal schematic diagram type v dss r ds(on) i d sts20nhs3ll 30v < 0.004 ? 20a(1) so-8 sales type marking package packaging sts20nhs3ll 20HS3LL- so-8 tape & reel rev. 2
sts20nhs3ll 2/9 table 3: absolute maximum ratings table 4: thermal data table 5: avalanche characteristics electrical characteristics (t j =25c unless otherwise specified) table 6: on /off table 7: dynamic symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v gs gate- source voltage 18 v i d(1) drain current (continuous) at t c = 25c 20 a i d drain current (continuous) at t c = 100c 12.6 a i dm (2) drain current (pulsed) 80 a p tot total dissipation at t c = 25c 2.7 w rthj-amb (3) t j t stg thermal resistance junction-ambient max maximum operating junction temperature storage temperature 47 -55 to 150 -55 to 150 c/w c c symbol parameter max value unit i av not-repetitive avalanche current (pulse width limited by t j max) 12.5 a e as single pulse avalanche energy (starting t j = 25c, i d = i av , v dd = 24v) 1.3 j symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1ma, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = 24v 500 a i gss gate-body leakage current (v ds = 0) v gs = 18v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 1ma 1 2.5 v r ds(on) static drain-source on resistance v gs = 10v, i d = 10a v gs = 4.5v, i d = 10a 0.0032 0.004 0.004 0.0055 ? ? symbol parameter test conditions min. ty p. max. unit g fs (4) forward transconductance v ds =15v, i d = 12a 30 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1mhz, v gs = 0 3950 720 70 pf pf pf 3/9 sts20nhs3ll electrical characteristics (continued) table 8: switching on table 9: switching off table 10: source drain diode notes: 1. this value is rated according to rthj-pcb 2. pulse width limited by safe operating area 3. when mounted on fr-4 board with 1 inch 2 pad, 2 oz of cu and t < 10sec 4. pulsed: pulse duration = 300s, duty cycle 1.5% symbol parameter test conditions min. ty p. max. unit t d(on) t r turn-on delay time rise time v dd = 15v, i d = 10a r g = 4.7 ? , v gs = 4.5v (see figure 15) tbd tbd ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =15v, i d =20a v gs = 4.5v (see figure 17) 27.5 7.9 8.7 37 nc nc nc symbol parameter test conditions min. ty p. max. unit t d(off) t f turn-off delay time fall time v dd = 15v, i d = 10a r g = 4.7 ? , v gs = 4.5v (see figure 15) tbd tbd ns ns symbol parameter test conditions min. ty p. max. unit i sd i sdm source-drain current source-drain current (pulsed) 20 80 a a v sd ( 4 ) forward on voltage i sd = 10a ,v gs = 0 0.7 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 10a, di/dt = 100a/s v dd = 25v, t j = 150c (see figure 16) 1.9 26 25 ns nc a sts20nhs3ll 4/9 figure 3: safe operating area figure 4: output characteristics figure 5: transconductance figure 6: thermal impedance figure 7: transfer characteristics figure 8: static drain-source on resistance 5/9 sts20nhs3ll figure 9: gate charge vs gate-source voltage figure 10: normalized gate thereshold volt - age vs temperature figure 11: normalized on resistance vs tem - perature figure 12: capacitance variations figure 13: normalized bvdss vs temperature figure 14: source-drain diode forward char - acteristics sts20nhs3ll 6/9 figure 15: switching times test circuit for resistive load figure 16: test circuit for diode recovery times figure 17: gate charge test circuit 7/9 sts20nhs3ll dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m 0.6 0.023 s 8 (max.) so-8 mechanical data sts20nhs3ll 8/9 table 11: revision history date revision description of changes 24-may-2005 1 first release 19-dec-2005 2 inserted curves 9/9 sts20nhs3ll i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subjec t t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are no t a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 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